This invention pertains to a data processing system having a host computer and at least one intelligent, mass storage, input-output (I/O) device and more particularly to an input-output interface bus for interfacing the host computer in such a data processing system to such an I/O device or devices.
The invention is particularly useful with but is not exclusively limited to use with high performance type I/O devices.
As used herein, the term "high performance I/O device" means any I/O device capable of transferring significant amounts of data with some frequency (e.g. a Winchester type hard disk drive or a streaming tape drive). As also used herein, the term "intelligent I/O device" means only I/O device capable of completing an I/O operation with only minimal support from the host resident controller (e.g. any I/O device capable of supporting an SCSI interface). As also used herein, the term "mass storage I/O device" means any device capable of storing significant amounts of data for extended periods, not immediately available to the host computer, (e.g. disk drives, tape drives and ram disks) but not main memory.
In data processing systems having a host computer and one or more I/O device, the transfer of commands, data and status information between the host computer and the I/O device is normally handled through a bus commonly referred to as an I/O interface bus. This I/O bus is normally connected to a resident controller in the host computer and is generally implemented in a physical backplane or cable, but it is the useage made of the various signals defined within the I/O interface bus which differentiates one I/O interface bus from the next. This invention is concerned with an improvement in this I/O interface bus.
Until now, I/O device interface busses have been designed to deal with only a single event and a single I/O device at any given time, (i.e. the bus has been used to communicate, in whatever fashion, with only one I/O device at a time) regardless of whether or not there is more than one I/O device connected to that bus and to transfer only one type of information to that I/O device at a time. Known prior art I/O busses such as SMD or ESDI deal with the I/O devices as a very low level, requiring the controller in the host computer to take charge of the actual, physical READ or WRITE operation, as well as converting the data between Serial and Parallel forms. Newer known prior art busses such as SCSI allow the controller to deal with the device at a higher level, leaving the control of the physical operation, as well as the data conversion, to the I/O device, while leading the controller free to assume a more efficient supervisory role.
All of the known prior art I/O busses share, to varying degrees, a common problem which is that, since the controller can only communicate with a single I/O device at any given time, any other I/O device must wait for that previous communication (or multiple communications) to be completed before its operation may be serviced. For example, if one I/O device begins an 8,192 byte data transfer at a transfer rate of 1,000,000 bytes per second, and a request is then given to the controller to access another I/O device, the controller will not be able to instruct the other I/O device to begin the operation until the first I/O device has finished its data transfer (8.2 milliseconds later). Generally, the largest amount of time involved in accessing these I/O devices is the initial SEEK (i.e. the positioning of the device to access the desired information) which does not involve any transfer of information beyond the initial command.
As can be appreciated, there is theoretically nothing to prevent the above two operations from being carried out at the same time (in parallel), except for the controller's inability to communicate the necessary information to the other device. The example noted above can be generalized to a system with any number of I/O devices, further aggravating this problem, with a concomittant loss in performance.
Accordingly, it is an object of this invention to provide a new and improved I/O interface bus for use in coupling a resident host controller to one or more of I/O devices.
It is another object of this invention to provide an I/O interface bus which is designed and arranged to allow a host resident controller to communicate with more than one I/O device at the same time.
It is still another object of the invention to provide an I/O interface bus which is designed and arranged to allow a host resident controller to transfer a plurality of different types of information to one or more I/O device at the same time.
It is yet still another object of this invention to provide an controller interface and an I/O device interface for handling information transfers as described above.
It is a further object of this invention to provide an I/O interface bus system for intelligent, high performance mass storage I/O devices.